| Author | Search for: Griffin, Ryan H1 |
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| Affiliation | - National Research Council of Canada. Information and Communication Technologies
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| Format | Text, Article |
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| Conference | LOPEC 2017, 28-30 March, 2017, Munich, Germany |
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| Abstract | A critical step in the production of integrated circuits (ICs) is layout versus schematic (LVS). The LVS process ensures that the interconnection of physical layers in the fabrication process of an IC matches the desired schematic. As circuit complexity increases, as is increasingly becoming the case for printed electronics designs, the need for LVS becomes paramount. Design errors in layout explode the cost of a project by wasting time and materials on a design bound to fail. Described herein are the extraction rules which allow LVS to be performed on multilayer printed electronics design with organic field effect transistors using standard IC design software, advancing the progress towards a complete integrated development environment for printed electronics. |
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| Publication date | 2017-03-29 |
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| Publisher | [The Conference] |
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| In | |
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| Language | English |
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| Peer reviewed | No |
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| NPARC number | 23002550 |
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| Export citation | Export as RIS |
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| Report a correction | Report a correction (opens in a new tab) |
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| Record identifier | c5134719-c0de-404f-9738-220b8c6360bd |
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| Record created | 2017-11-29 |
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| Record modified | 2020-03-16 |
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